1. Field of the Invention
The present invention relates to the electronics field. More specifically, the present invention relates to integrated electronic devices of the Silicon On Insulator (SOI) type.
2. Discussion of the Related Art
Electronic devices of the SOI type are integrated in a composite wafer, in which a buried insulating layer (such as of silicon oxide) separates two semiconductor layers (such as of mono-crystalline silicon). Particularly, the lower (thicker) silicon layer defines a common substrate; the upper (thinner) silicon layer acts as a starting layer, which is grown epitaxially to obtain an active layer housing the different electronic components (such as, MOSFET transistors) of the SOI device.
The oxide layer provides a robust voltage insulation of the components in the active layer from the substrate. Moreover, DTI (Deep Trench Isolation) processes may be efficiently employed to provide lateral insulation from adjacent components that are integrated in the same SOI device within different insulated regions of the active layer. In particular, such regions are fully insulated by means of the (buried) insulating layer and the DTI trenches. In addition, standard LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) processes may be used to provide a further lateral insulation of the components that are integrated in the same insulated region. Moreover, the SOI devices have other important advantages. For example, they do not suffer leakage effects between adjacent components. Moreover, the parasitic capacitances of the components integrated in the SOI device are significantly reduced.
Usually it is desired to maintain the substrate at a predetermined voltage (for example, to avoid undesired capacitive coupling effects). Particularly, when the substrate is not directly accessible from the backside of the SOI device it needs to be biased to the desired voltage through a corresponding contact formed on a front (upper) surface defined by the active layer. A typical example is an SOI device that is mounted on a chip carrier with a flip-chip technique, wherein the front surface of the SOI device faces the chip carrier (with its contacts that are directly connected to corresponding bumps of the chip carrier).
For this purpose, a via hole (or simply via) crossing the insulating layer of the SOI wafer is provided so as to connect the two silicon layers (i.e., the active layer and the substrate). Typically, the via is formed in a dedicated insulated region of the active layer and is connected to a corresponding contact arranged on the front surface.
In the state of the art such via is obtained by selectively etching the active layer so forming a trench extending from the front surface down to the substrate. The walls of the trench are then covered by a conformal conductive layer (i.e., such as to substantially follow the profile of the underlying structure), which conductive layer further extends on the front surface so as to define the desired contact.
A drawback of the solution described above is that each trench consumes a significant area of the SOI device. In fact, the trench must be wide enough to ensure that the conductive layer uniformly covers all its walls so resulting conformal (i.e., the trench has a significant so-called “step coverage”). This significantly increases the size of the whole SOI device.
A further problem of the SOI wafer is that the active layer can be affected by impurities, which impair the performance of the electronic components that are housed therein (and then of the whole SOI device).
In addition, the SOI wafer is typically used to integrate high-voltage electronic components (e.g., able to sustain voltages ranging from 50V to 250V); however, the same structure is not well suited to house low-voltage electronic components (e.g., able to sustain voltages ranging from 1.8V to 3.3V), for which a standard wafer with PN-junction insulation would be preferred. This problem is particularly acute for devices requiring both low-voltage and high-voltage electronic components.